The present invention relates to a liquid crystal panel and related method, and more particularly to a liquid crystal panel in which a thin film pixel driving transistors and thin film driver circuit transistors are integrated on a panel in a single process.
Large area and high resolution active matrix liquid crystal displays (AMLCD) include thin film transistors (TFTs) for driving individual pixels of the display pixels. TFTs are also incorporated into driver circuits for applying signals to gate bus lines and data bus lines coupled to the pixel driving TFTs of the display.
Generally, the driver circuit unit can be an integrated circuit attached to an outer portion of the substrate of the liquid crystal panel, and the driver circuit TFTs formed on the liquid crystal panel. Typically, the complementary metal oxide semiconductor TFTs (CMOS TFTs) with high field effect mobility are used in the driver circuits attached to the liquid crystal panel. Since this type of CMOS TFT consists of polysilicon (p-Si), the switching speed is much higher than that of amorphous silicon (a-Si). Further, because the driver circuit TFT and the pixel driving TFT are fabricated at the same time, the fabrication cost can be decreased.
FIGS. 1a-1h illustrate various steps of the conventional method of fabricating a typical liquid crystal panel including TFT driver circuits. For illustrative purposes in FIGS. 1a-1h, the driver circuit unit is shown divided into parts A and B.
As shown in FIG. 1a, a buffer layer 3 is first formed on the substrate 1 and then patterned a-Si semiconductor layers 4a, 4b and 4c are formed on the pixel and driver circuit portions. Semiconductor layer 4a corresponds to a transistor driving a single pixel and semiconductor layers 4b and 4c represent NMOS and PMOS TFTs formed on the driver circuit region.
As shown in FIG. 1b, an insulating layer 5 such as SiO.sub.2 and SiNx, a metal layer 6 such as Al, Al alloy, and Cr, and a photoresist 20a are successively formed on buffer layer 3. The insulating layer 5 and the metal layer 6 are patterned by a photolithography process to form gate insulating layer 5 and gate electrodes 6a, 6b, 6c. Low concentration n.sup.- ions are introduced into the entire area of the substrate 1, as shown in FIG. 1d, using gate electrodes 6a, 6b, 6c as masks over semiconductor layers 4a, 4b, 4c. As a result, portions of semiconductor layers 4a, 4b, 4c except those regions covered by gate electrodes 4a, 4b, 4c become doped n.sup.- layers 12b, and the regions under gate electrodes 4a, 4b, 4c become channel layers 12a.
Thereafter, photoresist layer 20b is deposited over substrate 1 and patterned to shield part B of the driver circuit region; gate electrode 6a, part of the activation layer, and an n.sup.- layer of the pixel region. As shown in FIG. 1e, n.sup.+ ions are introduced into the entire surface of substrate 1. In the pixel region, the width of photoresist 20b is larger than that of the gate electrode. Accordingly, the n.sup.+ ions are implanted into a part of the n.sup.- layer 12b. As a result, n.sup.+ layer 12c is formed in semiconductor layers 4a and 4b of the pixel region and part A of the driver circuit region. Further, the resulting transistor in the pixel region has an LDD structure including n.sup.+ layer 12c and n.sup.- layer 12b.
After photoresist 20b is removed, another photoresist layer 20c is deposited and patterned to shield the pixel region and part A of the driver circuit, as shown in FIG. 1f. P.sup.+ ions are then implanted into substrate 1, and p.sup.+ region 12d are thus formed in part B of the driver circuit. Regions 12d are doped with both p.sup.+ and n.sup.- ions, and are thus counter doped. Since the n.sup.- ion concentration is approximately 10.sup.16.about.10.sup.18 /cm.sup.3 and the p.sup.+ doping is about 10.sup.19.about.10.sup.21 /cm.sup.3, the n.sup.- layer 12b is converted into p.sup.+ layer 12d. Photoresist layer 20c is then removed.
Thus, the pixel region has TFTs with an LDD structure, including n.sup.+ layer 12a and n.sup.- layer 12b, and the driver circuit has NMOS TFTs having n.sup.+ layer 12c and PMOS TFTs including p.sup.+ layers 12d.
A contact hole is next formed in patterned SiNx insulation layer 7, as shown in FIG. 1g. A metal, such as Al, is then deposited on insulating layer 7 and into the contact hole to form source/drain electrode 8. Further, indium tin oxide (ITO) is deposited on the insulating layer 7 and source/drain electrode 8 to form a transparent pixel electrode 9 as shown in FIG. 1h. A passivation layer 10 is then provided blanketing the entire surface. In the liquid crystal panel fabricated according to the above described process, the pixel region has TFTs with an LDD structure and the driver circuit unit includes CMOS TFTs.
Although not shown in the figures, passivation layer 10 is patterned to form pad openings to interconnect the driver circuit region with an outer driver circuit attached to an outer portion of the substrate of the liquid crystal panel. Further, an alignment layer is formed on the passivation layer and rubbed mechanically to provide an alignment direction for the liquid crystal material. Further, another substrate is provided facing the above-described substrate, having color filters and a black matrix formed thereon to prevent light leakage.
In the above mentioned process, ten masks are used for patterning: the semiconductor layer, the n.sup.+ implant mask, the gate insulating layer and gate electrodes, the p.sup.+ implant mask, the contact hole, the source/drain electrodes, the transparent electrode, passivation layer pad openings, and black matrix. The conventional process, therefore, is complicated, the yield is reduced, and the fabrication cost is increased.